veditor is a Verilog and VHDL editor for Eclipse SDE. It is an open source plug-in with very nice set of features.
First, some words about other VHDL and Verilog editors. They can be found integrated into FPGA IDE as QuartusII from Altera, for instance, or ISE from Xilinx and no doubts - they are very good. Each has a free version of IDE (Web Edition or WebPack). This is how QuartusII IDE looks like:
I like Notepad++ very much for editing a single HDL file. Notepad++ is convenient and powerful as a general editor. In addition to that it understands many different languages including VHDL and Verilog: colorizes keywords and marks logical blocks of the languages:
An obvious disadvantage is that it does not show relationship between other files in a project.
Here veditor can become helpful. It can treat a bunch of files as a project
with all interconnections between files. That significantly simplifies editing.
In Outline window it shows all elements of an open file as interface, signals and components. It really helps with finding and jumping right to the element you want to edit.
Also veditor detects and shows up syntax errors and warnings, for example, about declared but not used signals and components:
To install veditor, download the latest version of the plug-in (I've got net.sourceforge.veditor_0.7.1.jar), then copy the file into "eclipse\plugins\" directory. Verilog/VHDL editor will be available for using after restarting Eclipse.